Event sequence detector

ABSTRACT

An event sequence detector is disclosed comprising a plurality of input units, each associated with a row of bistable elements arranged in an array of rows and columns. The detector also includes a shift register which is responsive to clock pulses from any of the units to sequentially provide enabling signals on its output lines each of which is connected to the bistable elements in a corresponding column. When an event-indicating signal is received by an input unit it provides a clock pulse to the shift register to provide the enabling signal on one of its output lines. The input unit also enables all its bistable elements so that the particular element in the column supplied with the enabling signal from the register is driven to an eventindicating state.

nited States Patent Fletcher et al.

EVENT SEQUENCE DETECTOR 3,524,185 8/1970 Ehni 340/415 3,613,092 10/1971Schumann 340/223 [76] Inventors: James C. Fletcher, Administrator ofNational Aeronautics and S ace 1 Administration with respectpto anPrimary Examiner-Thomas B. Habecker invention-of; Michael F. Hanna,AtwmeyfMonte Mon at 1213 Chesney Ave., Glendora, Calif. 91740 [57] 1ABSTRACT [22] Filed, Feb 4 1972 An event sequence detector is disclosedcomprising a plurality of input units, each associated with a row of [21Appl. No.: 223,560 bistable elements arranged in an array of rows andcolumns. The detector also includes a shift register which [52] U S Cl340/223 340/166 340/173 is responsive to clock pulses from any of theunits to se- 340/415 quentially provide enabling signals on its outputlines [5 I] lm Cl Gosh 23/00 Gosh 26/00 each of which is connected tothe bistable elements in 58 Fie'ld 340/223 415 a corresponding column.When an event-indicating signal is received by an input unit it providesa clock pulse [56] References Cited to the shift register to provide theenabling signal on one of its output lines. The input unit also enablesall UNITED STATES PATENTS its bistable elements so that the particularelement in 2,960,687 H960 Robison 340/223 the column supplied with theenabling signal from the register is driven to an event-indicatingstate. ien 3,523,278 8/1970 l-linkel 340/415 8 Claims, 7 Drawing Figures22 IO CLOCK 2 A Cl C 2 C 3 C X L l l i l I4A' A I A2 A3 AX 12 B B l3B il l l |4B:/l t. 8| B2 as .sx v I v 1" l l N1 N2 N3 NX Ol 02 O3 20 OX l ISll$2l$3| lsxl I Patented Sept. 18, 1973 3,760,394

4 Sheets-Sheet 2 LINE TERMINAL A OUTPUT OF GATE 26 I I CLOCK PULSE SFROM CLOCK 22 e I l l OUTPUT OF FF 24 f l i OUTPUT 0F FF 25 f o OUTPUTOF FF24 h E OUTPUT OF GATE l6 i l 7 OUTPUT OF ONE-SHOT 60 EVENT SEQUENCEDETECTOR ORIGIN OF INVENTION Aeronautics and Space Act of 1958, PublicLaw 85-568 (72 Stat. 435; 42 U.S.C. 2457).

BACKGROUND OF THE INVENTION 1. Field of the Invention The presentinvention is generally related to an event detector and, moreparticularly, to a detector for indicating the occurrence of events andtheir sequence of occurrence.

2. Description of the Prior Art There are many applications in which itis desired to detect the occurrence of events and their sequence ofoccurrence. For example, in testing complex instruments it is oftendesired to know which components or subsystems fail as well as the orderof the failures, wherein each failure represents a first event. This canbe achieved with a detector capable of detecting the occurrence'of thefirst event only in each source and the sequence in which these firstevents occur. Like wise, in a large automated system it is oftendesirable to monitor the performance of subsystems by determining whichsubsystems are activated as well as the sequence in which they areactivated. Assuming that each time a subsystem is activated itrepresents an event such monitoring can be accomplished by a detectorwhich is capable of sensing the occurrence of events in each of aplurality of sources and one which is further capable of indicating thesequence of occurrence of the various events in the various sources. Theprior artdoes not seem to disclose detectors having such capabilities.

OBJECTS AND SUMMARY OF THE INVENTION It is a primary object of thepresent invention to provide a novel event detector.

Another object of the present invention is to provide a novel detectorfor detecting the occurrence of events in a plurality of sources and thesequence of their occurrence. V

A further object of the present invention is the detection of thesequence of events in a plurality of sources.

Still a further object of the present invention is to de tect the firstevent in each of a plurality of sources and the sequence of theiroccurrence.

These and other objects of the present invention are achieved byproviding a detector including an input unit and a row of bistableelements for each source. In one embodiment, designed to detect thefirst event in a source the input unit is of the latchable type. When anevent-indicating signal is received from the source, the input unitenables'the bistable elements in the row and causes a clock pulse to beapplied to a shiftre'gister. Each stage of the latter is connected tocorresponding elements in the rows. The clock pulse causes the shiftregister to shift one stage and provide a clock pulse to a column ofelements, so that the particular element, enabled by its input unit andprovided with the clock pulse from the shift register, is driven to aneventdetection state.

,In another embodiment of the invention each input unit is capable ofresponding to a sequence of eventindicating signals. In this embodimentmore than one element in a row may be driven to its event-detectionstate during a monitoring period. At the end of the period the elementsin the event-detection state provide an indication of the number ofevents occurring in each source and the sequence of their occurrence.

The novel features of the invention are set forth with particularity inthe appended claims. The invention will best be understood from thefollowing description when read in conjunction with the accompanyingdrawings.

BRIEF-DESCRIPTION OF THE DRAWINGS FIG. 1 is a general block diagram ofone embodiment of the invention;

FIG. 2 is a detailed block diagram of an input unit 12A shown in FIG. 1;

FIG. 3 is a waveform diagram useful in explaining the embodiment shownin FIG. 1;

FIG. 4 is a partial block diagram of the embodiment shown in FIG. 1;

FIG. 5 is another embodiment of an input unit; and

FIGS. 6 and 7 are diagrams useful in explaining another embodiment ofthe invention.

- DESCRIPTION OF THE PREFERRED EMBODIMENTS '1 As seen from FIG. ll, inone embodiment the novel detector, designated by numeral 10 includes aplurality of input terminals A-N, although for simplicity only terminalsA, B and N are shown. The terminals are assumed to be connected to portsor subsystems A-N of a system, each subsystem being of the type in whichan event may occur, such as for example subsystem failure. Each event isassumed to be transduced to a logic level, such as true. Thus when atrue level is applied to a terminal it acts as an event-indicatingsignal from the subsystem or signal source to which it is connected.

Each terminal is connected to the input of a latching unit, designatedby numeral 12 followed by the terminals designation letter. Each unithas two output lines 13 and 14 followed by the suffix letter designatingthe unit. Thus the output lines of unit 12A are designated 13A and 14A.Included in the detector 10 is a plurality of event-indicating unitswhich are arranged in N rows A-N and X columns C1-CX. Each unit, such asAl, is designated by its row letter and column number. All the units inrow A are connected to line 13A while those in rows B and N areconnected to lines 133 and 13N, respectively.

The output lines 14A, 14B ..l4N are connected to a gate 16 with Ninputs. The output of this gate is connected to the input of amultistage shift register 20. For an X column array the registerincludes X stages Sl-SX with the output of each stage connected to theunits in a different array column.

In operation each latching unit responds to the first event-indicatingsignal received at the input terminal to which it is connected. Inresponse to this signal the level of the output line 13 changes to trueand remains true. Also, in response to the event-indicating signal thelatching unit 13 provides a pulse on line 14. This pulse in essencerepresents an event-reception pulse. The duration of this pulse iscontrolled by the rate of the clock pulses froma clock 22. Once thelevel of line 13 is set to true and the pulse is provided on line 14,the latching unit remains in a latched state inhibiting it fromresponding to subsequently received event-indicating signals and fromproducing additional pulses on line 14. However, line 13 remains trueuntil the detector is completely reset at the end of the test ormonitoring operation. One novel embodiment of the latching unit will bedescribed hereafter in conjunction with FIG. 2.

When one or more simultaneous pulses are applied to the inputs of gate16, the latter provides an output pulse which causes the shift registerto shift by one stage and supply an enabling signal on one of its outputlines to the units in the column connected to the particular line. Anyunit in the array which is connected to a line 13 in a true state and toa register output line on which an enabling signal is applied is drivento an event-indicating state, hereafter referred to as set.

Once a unit is driven to such a state it inhibits all subsequent unitsin its row from being driven to this state. Thus in the detector shownin FIG. 1, only one unit in each row can be driven to the set state. Inthis embodiment the maximum number of columns X is never greater than N.I

The foregoing description may be summarized wit a specific example.Initially all units and the stages of register are assumed to be in areset state. Let it be assumed that the first event-indicating signal isapplied to terminal B. Line 13B is set to true and a pulse is suppliedto gate 16 causing it to apply a shift or clock pulse to register 20.The first clock pulse which is supplied to the shift register causes itto apply an enabling signal on line 01. This enabling signal acts as aclock pulse and causes any unit in column C1 of the array which is alsoconnected to a true line 13, to be driven to its set state. In thepresent example since only line 133 is true only unit B1 is driven toits set state. Latching unit 128 is disabled from further supplyingpulses on line 14B to the gate 16 even though subsequently additionaltrue signals may be applied to terminal B. Also, once unit B1 is set itinhibits all subsequent units (B2-BX) from being set.

Assuming that the next event-indicating signal is applied to terminal N,latching unit 12N sets line UN to true and the pulse on 14N activatesthe gate 16, causing register 20 to provide an enabling signal on outputline 02. As a result unit N2 is set and it inhibits all subsequent unitsin row N from ever being set during the particular test.

Any event-indicating signals subsequently supplied to terminals B or Ndo not affect the detector since in each of these rows one unit isalready set and both latching units 128 and 12Nare latched. However, ifan event-indicating signal is applied to terminal A, it would latch unit12A. The supply ofa pulse to gate 16 would cause the register to providean enabling pulse on line 03. This pulse together with the setting ofline 13A to true would cause unit A3 to switch to its set state.

' At the end of the test operation the units in the array which are intheir set state indicate the sources of the event-indicating signals aswell as their sequence of arrival. In the particular example since unitsB1, N2 and A3 are set it indicates that at least one event-indicatingsignal was received at each of terminals B, N and A. Their sequence ofarrival is indicated by the columns in which the set units are located.In the particular example it is seen that the source connected toterminal B was the first to provide an event-indicating signal, whilethe source connected to terminal A is the last to have provided such asignal.

It should be pointed out that if event-indicating signal are applied totwo or more input terminals within the same clock period, two or morelatching units may become latched together and two or more units in thesame column of the array may be set, simultaneously. For example,assuming that the detector is reset and thereafter both terminals A andB are set to true during the same clock period, both units 12A and 12Bare latched. Thus, both lines 13A and 13B are set to true. Thesimultaneous pulses on line 14A and 14B activate gate 16 which providesa single pulse to the register 20, which causes an enabling signal toappear on line 01. Since lines 13A and 13B are both true, both units A1and B1 are set simultaneously. This indicates that terminals A and Bwere the first to receive eventindicating signals and that these signalsarrived simultaneously, i.e. within the same clock period.

Attention is now directed to FIG. 2 which is a diagram of one embodimentof the latching unit 12A, the other latching units being identicaltherewith. It includes a pair of JK flip-flops 24 and 25, NAND gate 26and an inverter 27. The 1 and 0 outputs of FFs 24 and 25 are connectedto lines 13A and 14A respectively and the input terminal A is connectedto one input of gate 26 while, the c (clock) input of FF24 is connectedto the clock 22. These flip-flops as well as all others to be describedherein are assumed to be clocked by trueto-false transitions at the 0inputs. It is apparent however that the transition or level required forclocking depend on the particular circuits which are employed andtherefore the example described herein should be regarded as but one.implementation of the teachings of the invention.

In the unlatched condition both FFs are reset, the output of gate 26 istrue and that of the inverter is false. When an event-indicating signalis applied at terminal A, at time t as shown in FIG. 3, line a, terminalA is at true level or simply true. Thus all three inputs of gate 26 aretrue and consequently its output becomes false (FIG. 3 line b) and thatof the inverter becomes true (line 0). When the trailing edge (i.e. thetrue to false transition) of the first clock pulse 30 (line d) is sensedat t it clocks FF24 and since its J input is true it sets F F24 so thatits 1 output is true (line e). As FF24 is set, its 0 output goes false(line g) and consequently gate 26 is set to true (line b) and that ofinverter 27 goes false. Also when line 14A, connected to the 0 output ofFF24, goes false it enables NAND gate 16 whose output goes true (lineh).

When the trailing edge of the next clock pulse arrives at FF24 is reset(lines e and g) and its 0 output goes true. Consequently, gate 16 isdisabled and its output goes false (line h). It is the true-to-falsetransition of the output of gate 16, represented in line h by numeral30, which serves as the clocking pulse for the shift register 20. Itshould be pointed out that FF25 remains set (line f). Thus line 13Aremains true from time t, on. Also since FF25 is set its 0 output isfalse. Thus NAND gate continues to provide a true output irrespective ofsubsequent changes in the level of terminal A from false to true.Consequently the latching unit remains latched until FF25 is reset atthe end of the test operation.

It should be noted that the two outputs of the unit are the continuoustrue output on line 13A and the false pulse 31 (line g) on line 14A whenFF24 is in its true state. The duration of this pulse is clearly afunction of the clock rate.

Attention is now directed to FIG. 4 which is a diagram of stages 81-83of shift register and units Al, A2 and A3 of row A, as embodied in oneembodiment of the invention. All stages following stage S3 are identicalwith stage S3 and all units following unit A3 are identical therewith.Likewise units in other rows are identical with those of row A. Stage S1comprises a flipflop (FF) 40, a NAND gate 41 and an inverter 42. StageS2 comprises FF44, a NAND gate 45 and an inverter 46, and stage S3comprises F F48, NAND gate 49 and' inverter 50. Unit A1 comprises a FF51and a NAND gate 52, while unit A2 comprises FF53, NAND gate 54 andinverter 55 and unit A3 comprises FF56, NAND gate 57 and inverter 58.All of the FFs are JK FFs assumed to be clocked by a true to falsetransitions and all the NAND gates are two-input gates except NAND gate57 which is a three-input gate.

Initially all FFs are reset. For explanatory purposes it is assumed thatthe first event is received at terminal A. At time t, (see FIG. 3) whenthe output of gate 16 becomes true, the output of gate 41 is false andthat of inverter 42 becomes true. Also line 13A becomes true. At time 1when the output of gate 16 goes from true to false, a clock pulse isapplied to all the FFs of the shift register. Since FFs 40 and 44 havetheir J inputs connected to the 0 output of 40 which is still reset,these two FFs are set. Also, the clock pulse from gate 16 switches gate41 to true and, therefore, the output of inverter switches from true tofalse, thereby applying a clock pulse on output line 01. Since line 13Ais true FFSl is set thereby indicating the detection of an event. Suchindication may be determined by connecting the 1 output of FF51 to anappropriate lamp, designated by numeral A1 which is illuminated whenFF51 isset. The l outputsof the other FFs of the array units are assumedto be connected to similar lamps each designated by the unitsdesignation, followed by a 0 subscript.

Once FFSl of A1 is set its 0 output is false. By. supplying it to gate54 of A2 whose output is in turn supplied to gate 57 of A3, thesubsequent units A2, A3 and all subsequent units in row A are inhibitedfrom being set, even though line 13A is true and even though pulses maybe applied subsequently to output lines 02-0X.

After the first pulse from gate 16 is received, FFs 40 and 44 remainset. Then when the next clock pulse is received fom gate 16, FF44 isreset and FF48 is set andthe true-to-false transition of the outputpulse of gate 16 causes gate 45 to provide a false-to-true transition,which in turn causes inverter 46 to provide a clock pulse (true-to-falsetransition) on output line 02. Thus successive pulses from gate 16 clockthe shift register to provide enabling signals or clock pulsessuccessively on its output lines.

As seen from FIG. 4, the various stages of the shift register aresubstantially identical. In each stage except 81, the FF is set when aclock pulse is supplied by the preceding stage and it is reset when aclock pulse is supplied by its stage. In stage S1 however FF40 is set bythe first pulse from gate 16 and remains set. Also, the various units inthe array (of rows and columns) are substantially identical except forminor variations in the inputs of the NAND gates.

It should be appreciated that the function fo the NAND gates and theinverters in the various units of the array is to inhibit subsequentunits from becoming set once a preceding unit is set to indicate anevent detection. Such an inhibiting arrangement is needed if the outputline such as 13A., of the latching unit 12A, remains true as long as theunit is latched. These NAND gates and inverters may however beeliminated if the duration during which a line 13 is true is limited andis caused to coincide with a clock pulse on oneof the output lines ofthe shift register. As shown in FIG. 5, the 1 output of FF25 of unit 12Amay be connected to a one shot 60 whose output is connected to line 13A.The one shot 60 is assumed to be triggered when FF25 is set, i.e., the 1output is true, to provide a true output to line 13A for a period whichis longer than one clock period. The true output of the one shot isdesignated by numeral 61 in line i of FIG. 3. The reason that the trueoutput has to be present for more than one clock period is to acount forthe delay produced by gate 16 and one stage of the register in producinga clock signal on one of the registers output lines in response to apulse on one of lines 14A.

Once the particular unit in row A which is supplied with the clock pulsefrom the register 20 is set, the level on line 13A returns to false.Since the unit 12A is of the latchable type FF 25 is only set once andtherefore the one-shot 60 provides only one true output, therebyenabling'the setting of only one unit in row A. Therefore, the variousNAND gates and inverters which interconnect the units in the row. arenot needed. It should be apparent that in such an embodiment a one-shotis connected between each input unit and its corresponding line 13. Thusthe elimination of NAND gates such as gates 52, 54, 57, etc., andinverters 55, 58, etc., is achieved atthe price of N one-shots.

Summarizing the foregoing description two embodiments of anevent-sequence detector have been described. In either embodiment, theinput unit (such as 12A) for each source is of the latched type. Whenthe first event-indicating signal is received from a source, the inputunit provides two output signals and thereafter the unit becomes latchedso that subsequent signals from the source cant be received. One outputsignal of the unit, represented by the false level 31 of the 0 out putofFF24 in line g of FIG. 3, is supplied to gate 16 for clocking the shiftregister. In one embodiment the other output is the true level of the 1output of FF25 and shown in line f. In this embodiment since this levelcontinues to be true, the various units of the matrix row to which thisoutput signal is supplied need be connected as shown in FIG. 4. This isnecessary to insure that once a unit in a'row is set all subsequentunits can 't be set.

In the other embodiment the second output signal of the input unit isthe output of the one-shot which is true for a limited duration only.The duration is chosen so that when a clock pulse is received on one ofthe output lines of the shift register; all the J inputs of the FFs inthe row are true. However, since the clock pulse is supplied only to oneFF, only it is set. Since the one-shot produces a true output duringonly one period or duration, only one unit can be set in each row.

Although in the foregoing embodiments each input unit, such as unit 12Ashown in FIG. 2, is assumed to be of the latched type, the invention isnot intended to be limited thereto. If desired each unit may be of theunlatched type. Such a unit is capable of responding to a succession ofevent-indicating signals from the source to which it is connected. Thiswould enable the detec tor to set more than one unit in each row.However, since the clocking of the shift register is subject to theoutputs of all the input units, the units which are set in each rowwould depend on the relative times of arrival of the event-indicatingsignals from the various sources. This embodiment may best be explainedin connection with FIGS. 6 and 7.

In FIG. 6, only an input unit connected to source A and the units of rowA together with gate 16 and the shift register 20 are shown. Basically,the input unit 70A comprises an input one-shot 71A which is connected toterminal A. The output of the one-shot is supplied to the k input of aJK FF 72A and through an inverter 74A to the J input of FF 72A. FF 72Ais clocked by clock pulses from clock 22. The clock pulses arediagrammed in line a, FIG. 7. When an event-indicating signal isreceived at at terminal A, as represented by the true pulse 75 on line bof FIG. 7, the one-shot 71A is enabled. It provides a false pulse 76(line of a selected duration. The duration is chosen to be somewhatlonger than one clock period. Thus the output of inverter 74A becomestrue, so that when clock pulse 77 arrives at 2 FF 72A is set (line d).When it is set its 0 output goes false (line e), enabling gate 16 asherebefore explained. Also the output of FF 72A is supplied to aone-shot 78A whose output (line 1) is connected by line 13A to all the Jinputs of units Al-AX. Oneshot 78A provides a true pulse 80 of aduration somewhat longer than one clock period. Then when the next clockpulse 81 arrives its trailing edge at t, resets FF 72A (lines d and e)so that the input unit is ready for the next event-indicating signal.Also the resetting of FF 72A causes the gate 16 to provide a true tofalse clocking transition for the shift register 20. It should beappreciated that in this embodiment the highest rate of event-indicatingsignals which can be sensed from any source is one half the clock rate.However, unlike the prior two embodiments in this embodiment more thanone unit in row A may be set during the test or monitoring period. Theinput units for the other sources are identical with unit 70A, eachincluding a FF70 followed by the sources letter designation. It shouldbe pointed out that since in this embodiment more than one unit may beset in any one row, the number of columns designated X may be greaterthan N.

The operation of this embodiment may be summarized in connection with aspecific examp e. Let us assume that eventindicating signals arereceived from the various sources during periods Pl-PS as shown in thefollowing table:

TABLE PERIOD SOURCE Pl A P2 D P3 B.C P4 DJ P5 A.E

It should thus be apparent that in column C1 of the array, correspondingto period Pl, only unit A] is set. Then unit D2 is set in column C2.When eventindicating signals from B and C are received during the sameperiod P3, both B3 and C3 are set. Then A4, D4 and E4 are set followingby the settings of A5 and E5. It is thus seen that in this embodimentall (rather than only the first) event-indicating signals from eachsource are monitored and detected by the number of set units in eachrow. Their times of occurrence relative to the occurrences of signalsfrom other sources is determined by which units are set in each row. Forexample, since in column Cl only Al is set, it indicates that the firstevent was received from source A. The second event from source A isindicated by the set A4. However, since this unit is in column 4 it isclear that the second event from source A arrived after the arrival ofthe first event from source D, represented by set unit D2 and after thearrivals of events from sources B and C, represented by the set units B3and C3.

Although particular embodiments of the invention have been described andillustrated herein, it is recognized that modifications and variationsmay readily occur to those skilled in the art and consequently it isintended that the claims be interpreted to cover such modifications andequivalents.

What is claimed is:

l. A detector for providing an indication of the sequence of occurrenceof events comprising:

n input terminals for receiving event-indicating signals from n sources;

a separate latching unit coupled to each input terminal the unit havingfirst and second output terminals providing a first continuous signal onsaid first output terminal and an event reception pulse on said secondoutput terminal only when the first event-indicating signal is receivedby its corresponding input terminal;

a plurality of element means arranged in an array of n rows and Xcolumns arranged in a sequence from 1 to X each element means beingdrivable between first and second states the elements in each row beingassociated with a different latching unit;

first connecting means for connecting the element means in each row tothe first output terminal of the latching unit with which they areassociated;

column control means having X output lines in a sequence from 1 to X,each coupled to the element means in a corresponding column;

means responsive to the event reception pulses on the second outputterminals at successive time periods for controlling said column controlmeans to provide successive enabling signals on its output lines, withan element means coupled to a first output terminal at which a firstcontinuous signal is applied and to an output line of said columncontrol means at which an enabling signal is applied being driven fromits first state to its second state; and

second connecting means for interconnecting the element means in eachrow so that when any element means in a row is driven to its secondstate all subsequent element means in that row are inhibited from beingdriven to said second state, X being not greater than n.

2. The arrangement as recited in claim 1 wherein the means responsive tosaid event reception pulses comprises a gate having n input terminalscoupled to the second output terminals of said n latching units forpro-v viding a control signal to said column control means whenever oneor more event reception pulses are simultaneously applied to its inputterminals.

3. The arrangement as recited in claim 2 wherein said column controlmeans comprises a shift register of X substantially identical stageseach including one of the output lines, said shift register beingresponsive to each enabling signal following a first enabling signalfrom said gate for sequentially shifting one of the stages thereof froma first state to a second state and a preceding stage previously in saidsecond state to said first state, with the preceding stage providing theenabling signal on the output line thereof.

4. The arrangement as recited in claim 1 further including a source ofclock pulses coupled to said n latching units, each latching unitincluding first and second flip-flops which are respectively connectedto said second and first output terminals of said latching unit.

5. An event sequence detector for detecting events in any of n sourcescomprising:

n input means each coupled to a different source with which it isassociated for providing first and second output signals for eachevent-indicating signal which is received from the source with which itis associated;

first means coupled to said n input means and responsive' to said firstoutput signals for successively providing enabling signals on aplurality of output lines thereof in response to a succession of one, ormore than one simultaneously received first output signals; and

switchable means including a separate sequence of elements associatedwith each input means and coupled thereto, with corresponding elementsin said sequences being connected to said output lines of said firstmeans, whereby in each sequence an element coupled to an'input meansproviding said second output signal and to an output line on which anenabling signal is applied switches'to an eventindicating state.

6. The arrangement as recited in claim 5 wherein said first meanscomprises gate means for providing a shift control signal when at leastone first output signal is supplied thereto, and a shift registercoupled to said gate means and responsive to each shift control signalfor providing successively said enabling signals on said output lines inresponse to a succession of said shift control signals.

7. The arrangement as recited in claim 6 wherein said switchable. meanscomprise an array of bistable elements arranged in rows and columns,with the elements in each row associated with a different input meansand responsive to the second output signal therefrom and the elements ineach column being associated with a different output line of said shiftmeans, an element switching to an event-indicating state only when asecond output signal is supplied by the input means with which it isassociated and an enabling signal is applied to the output line to whichit is connected.

8. The arrangement as recited in claim 7 further including clock meansfor clocking said n input means with clock pulses of a preselected clockperiod, whereby different input means which receive eventindicatingsignals from the sources with which they are associated during any clockperiod provide said first and second output signals simultaneously sothat bistable elements in rows associated therewith and in the samecolumn are switched simultaneously to said event-indicating state.

1. A detector for providing an indication of the sequence of occurrenceof events comprising: n input terminals for receiving event-indicatingsignals from n sources; a separate latching unit coupled to each inputterminal the unit having first and second output terminals providing afirst continuous signal on said first output terminal and an eventreception pulse on said second output terminal only when the firstevent-indicating signal is received by its corresponding input terminal;a plurality of element means arranged in an array of n rows and Xcolumns arranged in a sequence from 1 to X each element means beingdrivable between first and second states the elements in each row beingassociated with a different latching unit; first connecting means forconnecting the element means in each row to the first output terminal ofthe latching unit with which they are associated; column control meanshaving X output lines in a sequence from 1 to X, each coupled to theelement means in a corresponding column; means responsive to the eventreception pulses on the second output terminals at successive timeperiods for controlling said column control means to provide successiveenabling signals on its output lines, with an element means coupled to afirst output terminal at which a first continuous signal is applied andto an output line of said column control means at which an enablingsignal is applied being driven from its first state to its second state;and second connecting means for interconnecting the element means ineach row so that when any element means in a row is driven to its secondstate all subsequent element means in that row are inhibited from beingdriven to said second state, X being not greater than n.
 2. Thearrangement as recited in claim 1 wherein the means responsive to saidevent reception pulses comprises a gate having n input terminals coupledto the second output terminals of said n latching units for providing acontrol signal to said column control means whenever one or more eventreception pulses are simultaneously applied to its input terminals. 3.The arrangement as recited in claim 2 wherein said column control meanscomprises a shift register of X substantially identical stages eachincluding one of the output lines, said shift register being responsiveto each enabling signal following a first enabling signal from said gatefor sequentially shifting one of the stages thereof from a first stateto a second state and a preceding stage previously in said second stateto said first state, with the preceding stage providing the enablingsignal on the output line thereof.
 4. The arrangement as recited inclaim 1 further including a source of clock pulses coupled to said nlatching units, each latching unit including first and second flip-flopswhich are respectively connected to said second and first outputterminals of said latching unit.
 5. An event sequence detector fordetecting events in any of n sources comprising: n input means eachcoupled to a different source with which it is associated for providingfirst and second output signals for each event-indicating signal whichis received from the source with which it is associated; first meanscoupled to said n input means and responsive to said first outputsignals for successively providing enabling signals on a plurality ofoutput lines thereof in response to a succession of one, or more thanone simultaneously received first output signals; and switchable meansincluding a separate sequence of elements associated with each inputmeans and coupled thereto, with corresponding elements in said sequencesbeing connected to said output lines of said first means, whereby ineach sequence an element coupled to an input means providing said secondoutput signal and to an output line on which an enabling signal isapplied switches to an event-indicating state.
 6. The arrangement asrecited in claim 5 wherein said first means comprises gate means forproviding a shift control signal when at least one first output signalis supplied thereto, and a shift register coupled to said gate means andresponsive to each shift control signal for providing successively saidenabling signals on said output lines in response to a succession ofsaid shift control signals.
 7. The arrangement as recited in claim 6wherein said switchable means comprise an array of bistable elementsarranged in rows and columns, with the elements in each row associatedwith a different input means and responsive to the second output signaltherefrom and the elements in each column being associated with adifferent output line of said shift means, an element switching to anevent-inDicating state only when a second output signal is supplied bythe input means with which it is associated and an enabling signal isapplied to the output line to which it is connected.
 8. The arrangementas recited in claim 7 further including clock means for clocking said ninput means with clock pulses of a preselected clock period, wherebydifferent input means which receive event-indicating signals from thesources with which they are associated during any clock period providesaid first and second output signals simultaneously so that bistableelements in rows associated therewith and in the same column areswitched simultaneously to said event-indicating state.